MSP 2004, Memory Systems Performance June 8, 2004
Program

Accepted Papers

Paper Submission

Call for Papers

Important Dates


Committees




Preliminary Program
Tuesday June 8

9:00-10:00 Keynote: Jack Davidson

10:30-12:15 Session I Transformation

Instruction Combining For Coalescing Memory Accesses Using Global Code Motion, Motohiro Kawahito, Hideaki Komatsu, Toshio Nakatani (IBM Tokyo Research Laboratory)

Automatic Blocking Of QR and LU Factorizations for Locality, Qing Yi (Lawrence Livermore National Laboratory), Ken Kennedy (Rice University), Haihang You, Keith Symour, Jack Dongarra (University of Tennessee)

Metrics and Models for Reordering Transformations Michelle Strout, Paul Hovland (Argonne National Laboratory and University of Chicago)

1:30-2:30 Keynote: Kathryn McKinley

Polar Opposites: Next Generation Languages and Architectures,

2:30-3:40 Session II Memory Systems

Improving Trace Cache Hit Rates Using the Sliding Window Fill Mechanism and Fill Select Table, Muhammad Shaaban, Edward Mulrane (Rochester Institute of Technology)

An Empirical Performance Analysis of Commodity Memories in Commodity Servers, Darren Kerbyson, Mike Lang (Los Alamos National Laboratory),  Gene Patino, Hossein Amidi (Smart Modular Technologies Inc)

4:10-5:20 Session III Analysis and Language Support

Programmer Specified Pointer Independence, David Koes, Mihai Budiu, Girish Venkataramani, Seth Goldstein (Carnegie Mellon University)

Reuse-distance-based Miss-rate Prediction on a Per Instruction Basis,
Changpeng Fang, Steve Carr, Soner Onder, Zhenlin Wang (Michigan Technological University)