COMP8320 Tutorial 06 -- week 10, 2011
The Single-Chip Cloud Computer
Please read the articles mentioned below
before the tutorial.
The paper
The 48-core SCC
processor: the programmer's view is provided for reference on the
SCC.
Afterwards, discuss in small groups the following questions.
- What is meant by the term tera-scale computing
and what kind of applications are driving it?
- Give 2 reasons why the cores on a tera-scale system might be heterogeneous
(i.e. differ in terms of compute power and/or functionality).
- What energy management issues are there in manycore chips? In particular,
why might it be useful to reduce frequency for highly parallel workloads?
- Discuss the relative merits of the shared memory and message passing
programming paradigm, with respect to the metrics of validation
and composition.
- Why is the divide and conquer design pattern problematic
for the (distributed memory) message passing model?
- What is meant by the term collective communications?
(hint: you may need to look this up elsewhere; a reduction is an
example we have seen so far). Why do these present a problem
for the message-passing model? Why on the other hand is the
pipeline design pattern problematic for the shared memory model.
- What are the performance issues of supporting the shared memory
model in hardware? (see also Lecture
8).
As a group, we will go through the following distributed memory programming
concepts tha twill be required for the SCC:
- distributing a vector x of length N
over p processes (UEs)
- distributing an M by N
matrix C over a py by px
two-dimensional process grid.
- broadcast and reduction algorithms.
We will use the
block distribution in each case.
Last modified: 12/10/2011, 14:45
