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The Australian National University

Honours topics

Half of your time as an honours student is spent working on a project. But first you have to find a project topic.

The "official" reference for projects proposed by potential supervisors is the CECS projects database.

There are projects there available for all levels of research, including short projects, summerscholarship projects, Honours projects, Masters and PhD projects. All potential research students at any level are urged to browse it.

If you see a project that looks interesting, email the potential supervisor about it. Don't be afraid to discuss possible variations to the listed project: what appears on the web site is generally more of a suggestion than a rigid specification.

You don't have to be constrained by what you see on the project website. If you have something that you would like to work on as a project, then feel free to discus it with the honours convener to see if it could form the basis of an honours project and to identify a possible supervisor. Look at the web pages of Computer Science staff to find out their research interests. Remember that projects may also be supervised by people outside the College, or even ontside the University: from CSIRO or NICTA, for instance.

Former Project Topics

For your interest, here is an archive of Honours project proposals from previous years. Some of them are quite ancient now, of course, but they may help to give you ideas of the kind of thing which is suitable.
  • 2009 Proposed Project Topics
  • 2008 Proposed Project Topics
  • 2007 Proposed Project Topics
  • 2006 Proposed Project Topics
  • 2005 Proposed Project Topics
  • 2004 Proposed Project Topics
  • 2003 Proposed Project Topics
  • 2002 Proposed Project Topics
  • 2001 Proposed Project Topics


    2010 Honours project proposals



    Scalable Work Queues for Parallel Garbage Collection

    Physical limits mean that future performance improvements in processor design will mostly come from increased application-level parallelism. Thus the ability for systems to scale well on parallel architectures is an extremely important issue. Since managed languages such as Java and C# have become dominant in the application development domain, the scalability of managed runtimes has become a critical research issue. In this project we explore the scalability of a fundamental data structure at the heart of a Java runtime system---a load balancing parallel work queue.

    Supervisor: A. Prof Steve Blackburn, ANU

    Goals for this project

    This project will examine the scalability and pathologies of the load balancing parallel work queue used by MMTk, which is the memory management toolkit used by Jikes RVM. Hopefully the project will either confirm the scalability of the existing system or identify (and implement) a more scalable work queue design.

    Requirements

    Students will need to be proficient programmers with a good basic understanding of computer architecture and parallel algorithms. The work will all be done in a slightly restrictive subset of Java, so experience with Java is essential. Experimental design and data analysis is key to the first phase of the project, so experience in this area will be an asset (of course there will be plenty of assistance from your supervisor, particularly in this area).

    Student's gain

    The student will gain hands-on experience with an increasingly important problem in the context of the leading research infrastructure for managed runtime research, in the setting of a world leading team.

    Literature

    This is a well-focussed problem and does not require any significant background reading. The load balancing work queue is reasonably well insulated from the rest of the environment we work in, so a deep understanding of MMTk or Jikes RVM is not necessary. www.jikesrvm.org Contact Steve Blackburn

    Architectural Analysis of Garbage Collection Behavior

    Trends in microprocessor design are toward massively multicore chips. One direction within this burgeoning research area is that of asymmetric multicore design, where the cores within a chip are not homogeneous. In this setting some cores may serve very specific purposes. Given a) the centrality of garbage collection to managed runtimes, and b) the very limited requirements of garbage collection algorithms, it may make sense to have dedicated garbage collection cores. To this end, this project will explore the architectural "footprint" of a garbage collector with a view to ascertaining the base requirements for a dedicated garbage collecting core.

    Supervisor: A. Prof Steve Blackburn, ANU
    Goals for this project
    The project will use an architectural profiling tool (valgrind) to profile a range of garbage collection workloads and thus attempt to characterize the architectural requirments of garbage collectors.

    Requirements

    Students will need to be proficient programmers with a good basic understanding of computer architecture. The primary tool for this project will be valgrind, a publicly available virtualization tool written in C. The student working on this project should be an accomplished systems programmer.

    Student's gain The student will work on a problem of great industrial and academic importance and will gain a solid insight into the behavior of managed runtimes, at the architectural level. This project is a logical starting place for a much deeper examination of the project and eventually, realization in an FPGA. Literature
    A basic understanding of garbage collection would be helpful, but is not essential. Henessy and Patterson's standard text on computer architecture ("Computer Architecture: A Quantitative Approach", 4th edition) is an invaluable starting point for this work.

    Contact Steve Blackburn


    Profiling Java Virtual Machine Performance

    The performance of managed runtime systems and the applications which execute on them is a hot topic of academic and industrial research. However, dynamic compilation, feedback directed optimization, and concurrency each make performance analysis significantly more complex than in traditional ahead-of-time compiled, static environments such as C programs. This project will explore techniques for profiling the performance of virtual machines and applications running over them. These techniques will include sampling via interrupts (due to timers and/or hardware performance counter triggers) and direct instrumentation of compiled code. Additionally, the project will explore dynamic generation and maintenance of code annotations so that machine code and calling contexts can be tied back to source code in the application or VM source code.

    Supervisor:A. Prof Steve Blackburn, ANU
    Goals for this project This project will implement a number of different profiling techniques and a basic mechanism for dynamic maintenance of mappings between machine code and source code, in the context of Jikes RVM, a widely used research JVM.

    Requirements Students will need to be proficient systems programmers with a good C and Java skills.

    Student's gain The student will work on a problem of great industrial and academic importance and will gain a solid insight into the behavior of managed runtimes. The work will be carried out in a world-leading research group and will be conducted within the leading academic research infrastructure for managed runtimes.

    Literature and Background Familiarity with a simple profiling tool such as gprof would be an asset. Some interesting related work can be found at the following links: http://portal.acm.org/citation.cfm?id=1134012 http://www.cs.utexas.edu/users/mikebond/pcc-tr-2007.pdf Contact Steve Blackburn


    Bubble VM: the VM within the VM within the VM....

    Surprisingly, and despite the stated advantages of managed languages (such as Java and C#), no commercial managed runtime systems are written in the language they implement. However, there are two successful research runtimes which take this approach, Jikes RVM (an open source Java-in-Java VM), and Bartok (an ahead-of-time C# system on which the Singularity OS project is built). Both of these projects have demonstrated considerable promise, and both have demonstrated that performance need not be a roadblock to such VM implementations. One of the most vexing issues faced by such VMs is the potential for blurring the distinction between the application and the host on which it runs. In this project we will explore how to better understand the boundary between the application and the supporting VM, using a rough analogy to the isolation that exists between user mode and kernel mode in a modern operating system. A good understanding to this problem could fundamentally change the design of such JVMs, increasing their reliability, improving their debugability, and improving security. Such a VM could run on any other VM and could run any application---thus could be self hosting and in principle could host an arbitrary nesting of instances of itself within itself!

    Supervisor: A. Prof Steve Blackburn, ANU Goals for this project This project will start by trying to clearly identify the application-VM boundary in Jikes RVM, a widely used research JVM. The project will try to apply the OS metaphor of trapping from one context or mode to another. Depending on the student's ability and ambitions, the project could lead to much more ambitious goals such as enabling Jikes RVM to self host.

    Requirements
    Students will need to be proficient systems programmers with a good C and Java skills.

    Student's gain The student will gain a deep insight into the design and implementation of managed runtime systems. The work will be carried out in a world-leading research group and will be conducted within the leading academic research infrastructure for managed runtimes.

    Literature and Background
    There is not a great deal of prior work in this area. However, the original paper describing Jalapeno (which became Jikes RVM) describes some of the most basic issues that a Java-in-Java design must face: a Java-in-Java design must face Contact: Steve Blackburn


    Universal Artificial Intelligence (UAI)

    The dream of creating artificial devices that reach or outperform human intelligence is an old one. Most AI research is bottom-up, extending existing ideas and algorithms beyond their limited domain of applicability. The information-theoretic top-down approach pursued in [Hut05] justifies, formalizes, investigates, and approximates the core of intelligence: the ability to succeed in a wide range of environments [LH07]. All other properties are emergent.

    Goals of this project.
    The fundamentals of UAI are already laid out, but there are literally hundreds of open questions (see the exercises in [Hut05]) in this approach that have not yet been answered. The complexity ranges from suitable-for-short-projects to full PhD theses and beyond.

    Requirements.
    • background in AI or ML or statistics or information theory.
    • good math skills
    • good writing skills
    Student's gain.
    • getting acquainted with the most comprehensive theory of rational intelligence to date.
    • getting experience in writing a literature survey (if well done may be publishable), -or-
    • learn how to prove non-trivial theorems.
    Literature
    • [Hut05] M. Hutter. Universal Artificial Intelligence: Sequential Decisions based on Algorithmic Probability Springer, Berlin, 2005.
    • [LH07] S. Legg and M. Hutter. Universal intelligence: A definition of machine intelligence. Minds & Machines, 17(4):391--444, 2007.

    Reasoning in Artificial Intelligence

    PDF document
    Supervisor: Jinbo Huang

    Implement a Personal Energy Meter

    Supervisor: Tom Worthington

    Use a mobile phone to track users, calculating how much energy they are using, for energy reduction planning.

    Simon Hay has proposed "A Global Personal Energy Meter" at the University of Cambridge Computer Laboratory: .

    This project would attempt to simplify Mr. Hay's approach and apply it in a practical setting.

    The student may work with those undertaking the postgraduate course "Green Information Technology Strategies" (COMP7310), estimating carbon emissions in a range of government, industry and academic settings: .

    See also: "Green Technology Strategies", Tom Worthington, 2009: .


    Migrating Applications to the Cloud

    Many organisations are looking to Cloud Computing to reduce costs and improve efficiency of their applications. There are various strategies ranging from design-time use of the cloud to partition systems/applications to run on the cloud to dynamic/runtime use of the cloud through the use of “Cloud Bursts”.

    We are investigating what are the complete set of existing strategies, what is actually involved in the various strategies, and what are the costs and benefits of the various strategies.

    We have several projects to explore this area in more detail.

    Supervisor: Liam O'Brian

    Slides

    Web Service Management System (several projects) Supervisors: Wanita Sherchan, Surya Nepal (CSIRO)

    Project descriptions
    Slides (ppt)

    Mars Rovers and Traffic Controllers

    Supervisor: Scott Sanner

    News Search Summarisation

    Supervisor: Scott Sanner

    Slides (pdf)

    Smartcard-enabled Android mobile phone as a "security token" for a PC

    Smartcards are able to provide strong authentication on the Web through integration with a user's browser, which is usually achieved through a smartcard reader physically attached to the user's PC. On the other hand, a convenient and effective approach to authentication on the Web, often used in online banking, involves the use of a user's mobile phone as a one-time password token. However, unlike smartcard authentication, such a scheme cannot defend against a man-in-the-middle attack such as phishing.

    A scheme which involves both smartcards (security) and mobile phones (ubiquity and convenience) to secure PC-to-Web communications is an intriguing possibility. This could, for instance, involve a smartcard-enabled mobile phone application connected to a user's browser (over the Internet) playing the role of a security token for the browser. A recent announcement by a major smartcard manufacturer to support mobile phones, through development of Micro SD Card form-factor smartcards and open source Android software support, makes this a timely investigation.

    This project will have research as well as implementation components. A pre-requisite is a strong understanding of networking and Internet security; in particular, an ability to understand security protocols. Strong familiarity with Linux and Java are pre-requisites for the Android implementation component.

    Supervisor: Ming Yung (CSIRO)

    Designing and prototyping Android mobile phone applications secured with a smartcard

    The open source Android mobile phone "stack" promoted by Google is increasingly seen as a strong competitor in the "smartphone" category. G&D, a major smartcard manufacturer, recently announced that they are building smartcards for mobile phones, using the Micro SD Card interface, and are providing Android software support for interacting with these smartcards. This opens up the opportunity for development of mobile phone applications (on Android) which are strongly secured.

    This project will involve implementation of smartcard-enabled Android applications. It will involve programming on the Android platform as well as smartcard chip programming. Because the Android smartcard project at Google Code is still under very active development, it is expected that there will be opportunities to contribute code towards that project. Strong familiarity with Linux and Java are pre-requisites.

    Supervisor: Ming Yung (CSIRO)

    Implementing U-Prove anonymous credentials on a Java Card smartcard

    Anonymous credential schemes are designed for authentication of user attributes while preserving user anonymity. As such they have been proposed for use in "identity systems" which have built-in privacy protection. One such scheme, designed by IBM and associated with its Identity Mixer technology, was recently implemented on a Java Card smartcard by two groups (IBM Zurich and K U Leuven) independently. An alternative scheme is U-Prove, invented by Stefan Brands (a pioneer in privacy-enhancing technologies) but now owned by Microsoft.

    This project will investigate the feasibility of implementing U-Prove on the Java Card platform. It will suit a student who is able to understand the mathematics behind anonymous credential schemes and who is keen to program in the resource-constrained Java Card environment. Strong familiarity with Linux and Java are pre-requisites.

    Supervisor: Ming Yung (CSIRO)

    Publication Venue Ranking: A Portal and Query Tool

    For funding agencies, research agencies, universities and researchers, assessing the quality of a publication venue is important. Assessors use such rankings to assess the quality of an individual or institution's research output. Researchers use such rankings to gauge at which venue their work might see greatest impact. Prompted in part by the ARC (the Australian Research Council), Australian computer scientists have produced a ranking of publication venues which is now used by over 20 countries. This project is moving into a new phase, where a key component will be a publication ranking portal, which will allow individuals and agencies to rank publication venues according to a variety of criteria. Ideally, users will be able to create their own ranking criteria based on the various per-venue metrics gathered and maintained by the portal. ANU (Steve Blackburn) is leading this project and chairing the ranking committee on behalf of CORE (http://www.core.edu.au/ ).

    Supervisors: A. Prof Steve Blackburn, ANU; Prof. David Hawking, Funnelback; Dr Paul Thomas, CSIRO

    Goals for this project:

    This project will prototype a ranking tool, spidering tools, and explore various ranking criteria within the new venue ranking portal.

    Requirements:

    Students will need to be proficient programmers, preferably with a good grounding in databases including some proficiency with SQL.

    Student's gain

    This is a broadly defined project that provides a variety of opportunities for the student, depending on the student's enthusiasms and aptitude. The student will work on a world-first system for ranking publication venues. The project will include input from Prof Hawking, Dr Thomas, and other information retrieval experts based at ANU and CSIRO.

    Contact: Steve Blackburn

    Micro-Architectural Analysis of JavaScript Performance

    JavaScript has become the "assembly language of the internet", providing portability and ubiquity to trivial and complex applications alike. JavaScript performance has become a red-hot issue, with companies like Google, Mozilla and Microsoft spending considerable resources on JavaScript performance. However, JavaScript applications are in many regards rather different from traditional workloads to which current hardware has been tuned.

    Supervisor: A. Prof Steve Blackburn, ANU

    Goals for this project:

    This project will conduct a micro-architectural analysis of JavaScript performance in order to understand how better to tailor architectures to the particular needs of JavaScript. The outcomes of this project may include how better to configure caches, branch predictors and functional units for good JavaScript performance.

    Requirements:

    Students will need to be proficient programmers with a good understanding of the basics of computer architecture. Understanding and being able to program in JavaScript will be useful, but not essential. You will work within a cycle-accurate x86 simulator. Experimental design and data analysis is key to the first phase of the project, so experience in this area will be an asset (of course there will be plenty of assistance from your supervisor, particularly in this area).

    Student's gain:

    The student will gain hands-on experience with an increasingly important problem. The student will work in the context of the leading research infrastructure for managed runtime research, backed up by a great research team. The project has sufficient depth and scope to allow a capable student to produce publishable work.

    Literature:

    This is a well-focussed problem and does not require any significant background reading. Patterson and Hennesy's classic text will provide a good grounding to this project.

    Contact: Steve Blackburn

    Evict-Me And Other Interesting Cache Semantics

    Memory performance is key to application performance. Caches typically implement an approximation to an LRU (least recently used) eviction policy, with the goal of evicting that data which is least likely to be used next. However, there exist important use-patterns which do not play well to LRU. One such example, is the case where data is used very briefly then discarded. In previous work our colleagues developed the "evict-me" policy which allows the application to provide a hint to the cache that a given cache line should be evicted. This proved to be useful in a number of situations, however the idea was not evaluated against Java (or other managed language) workloads. We believe that programing languages such as Java which encourage high allocation rates may be well suited to evict me and similar such policies. In our prior work we noted that many Java applications allocate many objects that are only used very briefly. Such objects would be very good candidates for evict-me.

    Supervisor: A. Prof Steve Blackburn, ANU

    Goals for this project:

    This project will examine the effectiveness of special ISA-supported cache semantics in the context of a high allocation rate language such as Java.

    Requirements:

    Students will need to be proficient programmers with a good basic understanding of computer architecture.

    Student's gain:

    The student will have the opportunity to gain in-depth experience in a significant research problem that crosses two research fields. The project has sufficient depth and scope to allow a capable student to produce publishable work.

    Literature: Follow this link Contact: Steve Blackburn

    Formal Security Proofs via SAT solving

    Supervisor: Dr Alwen Tiu (Logic and Computation group, CECS)

    A security protocol is a sequence of message exchanges between parties in a network system, usually used to establish certain security targets such as authentication, exchanges of session keys, etc. The problem of finding an attack on a security protocol (under certain security assumptions) is undecidable in general. However, it has been shown that if the number of sessions of the protocol is bounded, then the problem is solvable in NP. In this project, we will look at uses of modern propositional satisfiability solver (SAT) to decide (in)security of a security protocol. Since protocol insecurity is in NP, the problem of finding an attack on a protocol can be mapped to the propositional satisfiability problem. A particularly interesting problem is how to obtain a proof of security, in the form of a propositional refutation. We will experiment with different SAT solvers that produce explicit resolution proofs (in case of unsatisfiability) and extract security proofs from them. One of the aims is to extract small security proofs which can be efficiently verified. We will experiment with extracting security proofs for a range of industrial security protocols, especially those that have been standardised or undergoing standardisation by th Internet Engineering Task Force (IETF).

    At a more advance stage of the project, we will look at formal verification of the mapping from security problems into SAT and reconstruct the security proofs found by SAT solvers in a proof assistant. There is possibility to turn this project into a PhD topic.


    Real-time point-to-surface image registration on the GPU for medical applications

    Word document

    A common problem in image guided surgery is the registration of a pre-operative 3D image such as a CT scan or an MR image with the physical position of the patient. The solution typically involves collecting position data from the body using a calibrated probe and registering the recorded point cloud with the 3D image. This point-to-surface registration problem can be efficiently solved using the 'iterative closest point' (ICP) algorithm. The purpose of this project is to develop a real-time point-to-surface registration tool through an efficient implementation of a nearest-neighbour search on the GPU using a kd-tree data structure.

    At the end of the project, the student will have learned GPU programming (including CUDA and OpenCL), the basic concepts of medical image registration, the ICP algorithm, and the kd-tree data structure. Efficient implementation of a kd-tree-based search on the GPU is not trivial due to the need to traverse a binary tree which in practice is not balanced while making sure that all computational resources are being utilised and also due to lack of native support for a stack in a GPU kernel.

    The project is associated with a major ARC Linkage project involving five ANU academics, the Microsoft Beijing Research Laboratory and a Microsoft incubator group located in Redmond, USA. The work is expected to lead to one or more publications with the ARC grant providing funding to support presentation of this work at a conference.

    Supervisors: Dr. Ramtin Shams, A/Prof Alistair Rendell (contact ramtin.sharma@anu.edu.au

    Automated reasoning in modal logics

    Supervisor Rajeev Gore and Alwen Tiu

    See PDF document for description

    Proof-theory of non-classical logics

    Supervisor Rajeev Gore and Alwen Tiu

    See PDF document for description

    Fast and optimal path-finding on grid maps

    Path-finding is the task of computing a path to a target on a map. It has many applications, including games, robot navigation and itinerary planning. The problem is usually addressed by running a search algorithm, such as A*, on a grid or other graph representation of the map.

    The aim of this project is to develop an algorithm for generating optimal paths quickly and with limited memory use. A standard search algorithm visits all neighbours of a currently expanded cell. In this work, to avoid exploring portions of the map that are irrelevant to the search at hand, the set of visited neighbours is restricted using a set of rules based on local topological information.

    The main contributions of the student will be as follows:

    • Refine the rules starting from an original idea suggested by the supervisors.
    • Prove the correctness of the rules with respect to maintaining the completeness and the optimality of the search strategy.
    • Implement a search algorithm that integrates the set of rules. A C++ code base called HOG is available. An animation of HOG is available here. However, the student may choose to develop the algorithm from scratch or on top of a different code base.
    • Perform an experimental analysis of the algorithm.
    There is a possibility to turn this project into a PhD topic.

    Supervisors: Adi Botea and Alban Grastien

    Implementing the SCAM Climate Code on a Graphics Processing Unit

    Supervisoa:r Peter Strazdins

    See the project description


    Automatic Tuning of the High Performance Linpack Benchmark

    Supervisoa:r Peter Strazdins

    See the project description


    Parallelizing the Gravitational N-body Problem on a Heterogeneous Cluster

    Supervisoa:r Peter Strazdins

    See the project description


    Exploring Multicore Software Engineering

    Supervisoa:r Peter Strazdins

    See the project description


    Exploring the UltraSPARC T2's Multicore Cryptographic Capabilities

    Supervisoa:r Peter Strazdins

    See the project description


    A Dynamic Logic for Graph-transformation Systems

    Model Driven Development allows developers to use UML models to visualise the structure of software and to generate code automatically. Although most programmers have a very good idea of how their code is going to execute, it is much more difficult to understand the runtime behaviour of a model. Since most UML models can be seen as graphs, which possibly evolve over time, Graph Transformation Systems can provide a clearer definition of modelling languages such as UML.

    The project is to design a logic for reasoning about graph transformation using a graph-transformation system. The logic will most likely extend a well-known programming logic called Propositional Dynamic Logic so the task is not as difficult as it appears. As usual, a host of questions then arise like: is the logic decidable; if so, what is the computational complexity; can we implement it on a computer; can we define a reference animator based upon this logic?

    Supervisors: Rajeev Gore with Greg O'Keefe (DSTO) and Linda Postniece

    Background: You will need a familiarity with UML and a strong background in discrete mathematics. You will have to learn about modal logic and graph-transformation systems.

    Future: This project will set you up for a Phd in theoretical computer science and may lead to a publication in an international conference. It is highly likely to lead on to a Phd if you wish.


    Investigation of Prefetch Strategies for Cluster OpenMP

    Supervisor: Peter Strazdins

    See the project description


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