ANU Computer Science Technical Reports

TR-CS-05-01

Peter Strazdins.
CycleCounter: an efficient and accurate UltraSPARC III CPU simulation module.
May 2005.

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Abstract: This paper presents a novel technique for cycle-accurate simulation of the Central Processing Unit (CPU) of a modern superscalar processor, the UltraSPARC III Cu processor. The technique is based on adding a module to an existing fetch-decode-execute style of CPU simulator, rather than the traditional method of fully implementing the CPU pipeline and microarchitecture. The main functions of the module are the simulation of instruction grouping, register interlocks and the store buffer, and has a simple table-driven implementation which permits easy modification for exploring microarchitectural variations. The technique results on a 15-30% loss of simulation speed, instead of a 10 × or greater performance loss by fully implementing the detailed micro-architecture. The accuracy of the technique is validated against an actual UltraSPARC III Cu processor, and achieves high levels of accuracy in cases of interest.

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Last modified: Tue May 31 12:56:01 EST 2011