We will use two textbooks in this course.
We will use the fifth edition of this famous Patterson and Hennessy book. This book has three primary variants. The main difference is the specific instruction set architecture (ISA) they use to teach processor design fundamentals. In this course, we will use the MIPS ISA version. Other versions use the ARM and RISC-V ISA. Most details are retained across the three versions.
All three ISAs use a 32-bit fixed-width instruction format. The book takes a subset of the ISA in all three cases and composes two implementations of an in-order processor: (1) single-cycle and (2) pipelined. It then discusses performance hazards in the two implementations. If you use a different version of the book than our course uses, please watch out for how the instruction bits map to the control and data lines in the diagrams in chapter 4 (weeks 4 to 6).
We will use the sixth edition of this second book (also from Patterson and Hennessy) and discuss selected sections from the first three chapters. Specifically, we will use this book to understand how best to transform the in-order pipeline into a high-performance out-of-order pipeline. Our discussions on dynamic instruction scheduling and hardware speculation after the teaching break will primarily rely on Chapter 3 of the book. We will also discuss (time permitting) two flavors of out-of-order design used by Intel and AMD processors. Finally, we will use this book to examine more sophisticated branch predictors. On the memory side, this book offers advanced techniques to optimize the cache hierarchy.
Other useful introductory books
Digital Design and Computer Architecture This book from David Harris and Sarah Harris provides a richer bottom-up approach to processor design fundamentals. It begins with an excellent background on combinational and sequential logic fundamentals before implementing the MIPS/ARM ISA.
The RISC-V Reader: An Open Architecture Atlas This book from David Patterson and Andrew Waterman provides an excellent introduction to the emerging open-source RISC-V ISA. The introductory chapters offer an insight into the implications of ISA design for high-level programming languages and processor implementation details. We will partly base our discussion on ISA design during the third week on selected material from this book.
Modern Processor Design: Fundamentals of Superscalar Processors
Authors: John Paul Shen and Mikko H. Lipasti
Processor Microarchitecture: An Implementation Perspective
Authors: Antonio Gonzalez and Fernando Latorre and Grigorios Magklis
S1: Computer Organization and Design: The Hardware/Software Interface (5e)
S2: Computer Architecture: A Quantitative Approach (6e)
S3: Research papers and slides
|Week & Topic||Textbook Chapters||Other|
|7/26, Introduction||Chapter 1 (S1 and S2)||S3|
|8/9, ISA||Chapter 2 (S1)|
|8/16, Single-Cycle uarch||Chapter 4 (S1)|
|8/23, Pipelined uarch||Chapter 4 (S1)|
|8/30, Hazards||Chapter 4 (S1), Chapter 3 (S2)|
|9/20, ILP-1||Chapter 3 (S2)|
|9/27, ILP-2||Chapter 3 (S2)||S3|
|10/4, Caches-1||Chapter 5 (S1)||S3|
|10/1, Caches-2||Chapter 3 (S2)||S3|
|10/18, DRAM||Chapter 5 (S1)||S3|