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Assignment will become valid and submissions will open in week 8 at the latest (exact date will be announced in the lecture and forum). Before that they are sneak-previews to give you an idea about the events to come (and can still change).

Assessment Tasks Sources Background Time frame & deadline

Assignment: Synchronized Generators


For your hard real-time experiments:


ARM board

168 MHz, 32-bit ARM Cortex-M4F Core, 1 MB Flash, 192 KB RAM,
3-axis accelerometer, audio interface with class D speaker driver, USB OTG FS,
12x 16-bit timers, 2x 32-bit timer, Watchdog timer, 16x DMA channels,
2x CAN, 3x I2C, 3x SPI, 6x UART's, IEEE1588,RTC, PLL,

2x 12-bit DAC, 3x 12-bit ADC,
Nested vectored interrupt controller,

on top of: ANU Real-Time course base board (designed by PhD student Mark Turner)



Controller background:
pdf document Reference manual

pdf document Data sheet
pdf document ANU base board schematics
pdf document Discovery kit user manual



pdf document Synchrony

Haskell source file Code framework


4 weeks

Deadline: Friday, 18th October, 23:59:59

Writing hints: link

Typesetting hints: link



Updated:   Friday 18 October, 2019 8:14 / Responsible Officer:   JavaScript must be enabled to display this email address. / Page Contact:   Course Webmaster